1. Field of Invention
The present invention relates to a single wire transmission interface, and also to a method for single wire transmission.
2. Description of Related Art
Current transmission interfaces such as I2C, SPI, SMBUS require at least two wires, of which one is for data transmission and one is for clock transmission. If a single wire is capable of achieving both data and clock transmission, the pin number can be reduced. Hence, prior art U.S. Pat. No. 7,127,631 discloses a method for single wire series transmission and can be used for setting an internal operation mode or other parameters inside an integrated circuit. The method disclosed in the prior art is shown in FIG. 1, wherein when a receiving side detects a rising edge of an EN/SET signal, it is enabled to receive data (as shown by the waveform Enable) and generate a decoded signal (as shown by the third waveform) corresponding to the EN/SET signal; simultaneously, a counter at the receiving side starts counting the rising edges of the EN/SET signal (1˜n). When the receiving side detects a falling edge of the EN/SET signal, it starts counting a time-out period (Time Limit). If the receiver side does not detect a next rising edge within the time-out period, it will shut down the signal Enable, reset the counter, and set the decoded signal to low.
In the foregoing prior art, when the time limit is reached, the count is reset and the decoded signal returns to the low level. However in certain applications, such arrangement is not necessary, or even undesired. After the time limit is reached, the decoded signal should be capable of staying at any level, such that a next-stage circuit can make different uses of it.